{"id":551,"date":"2021-01-21T05:25:37","date_gmt":"2021-01-21T05:25:37","guid":{"rendered":"http:\/\/www.vk2sja.org\/piffle\/?p=551"},"modified":"2021-01-21T06:44:19","modified_gmt":"2021-01-21T06:44:19","slug":"pisc-conditional-jumps","status":"publish","type":"post","link":"https:\/\/www.vk2sja.org\/piffle\/2021\/01\/21\/pisc-conditional-jumps\/","title":{"rendered":"PISC – Conditional Jumps"},"content":{"rendered":"

The first of the “Glaring Deficiencies”<\/em> in need of a solution was the missing conditional branch (jump). This is how I went about solving it. Firstly a review of how PISC encodes an instruction:-<\/p>\n

\n

\u00a0\u00a0\u00a0\u00a0\u00a0\u00a0\u00a0\u00a0\u00a0\u00a0\u00a0\u00a0\u00a0\u00a0\u00a0\u00a0\u00a0\u00a0\u00a0\u00a0\u00a0\u00a0\u00a0\u00a0\u00a0\u00a0\u00a0\u00a0\u00a0 IR 15:0<\/strong>
\nMRD\u00a0 MWR ARGx3 DRGx3 LTS\/ CY-IN ALUx5<\/strong>
\n\u00a0\u00a0 1\u00a0\u00a0\u00a0\u00a0\u00a0\u00a0\u00a0 0\u00a0\u00a0\u00a0\u00a0\u00a0 111\u00a0\u00a0\u00a0\u00a0 xxx\u00a0\u00a0\u00a0\u00a0\u00a0 1\u00a0\u00a0\u00a0\u00a0\u00a0\u00a0\u00a0 11 \u00a0 0-0000 \u00a0\u00a0\u00a0\u00a0\u00a0\u00a0<\/strong><\/h2>\n<\/blockquote>\n

A sixteen bit instruction where:-<\/p>\n

MRD   = Memory\/IO Read\r\n\r\nMWR   = Memory\/IO Write\r\n\r\nARG   = Address Bus Register Select x 3 bits (ALU A Input)\r\n\r\nDRG   = Data Bus Register Select x 3 bits (ALU B Input)\r\n\r\nLTS\/  = Latch Status (Both CY & EQ) when low\r\n\r\nCY-IN = Carry In Signal Select x 2 bits\r\n\r\nALU   = ALU Function x 5 bits<\/pre>\n
The actual values above are taken from Brad’s original paper<\/a> and are in fact the hard coded Fetch Instruction. The data bus register select is shown as “xxx” <\/em>for “don’t care” <\/em>because during the Fetch Cycle the normal write to Register File (port C-in) is inhibited and the data bus contents are instead latched into the “Instruction Register”. <\/em>If one looks to the actual circuit diagram<\/a> for PISC 1.0a we can see that this register select happens to be wired all high (R7). So the actual Fetch Instruction is:-<\/p>\n
10111111 11100000 <\/strong>or $BFE0
\n<\/strong><\/p>\n
This instruction translates to:-<\/p>\n
    \n
  1. Read memory (destination is the Instruction Latch during fetch cycle).<\/li>\n
  2. Address Register set to R7 (the Program Counter).<\/li>\n
  3. Do NOT latch the status bits (high)<\/li>\n
  4. CY-IN Select = ’11’ which is a numerical one “1” indicated by a logic low.<\/li>\n
  5. The five 74181 ALU Function Bits correspond to “Arithmetic Operation F=A+CY<\/li>\n<\/ol>\n
    So the result is that the register R7 the Program Counter is used as the address to read and is then post incremented because the CY-IN is hard selected for a “1”.<\/p>\n
    Probably also worth showing the Carry-In select truth table for the original PISC 1.0a at this point:-<\/p>\n
    00 = CY\r\n01 = EQ\r\n10 = \"0\" (logic level high)\r\n11 = \"1\" (logic level low)<\/pre>\n
    Now that all this is behind us let’s get down to the details of the modification. From Brad’s original paper he observes that the 74181 can be selected for either a Logic or Arithmetic operation. This is controlled by IR:4 which I separated out above as the leading “0-”\u00a0<\/strong>in the fetch instruction to make it stand out.<\/p>\n
    Brad goes on to make the important observation that if IR:4 is set high for a logic operation then the CY-IN selection bits IR:6 and IR:5 are irrelevant because the Carry-In is not used for logic operations. So this is where we shall implement our conditional branch.<\/p>\n
    We are going to arrange it such that “if a carry-in *is* specified for a logic operation”<\/strong><\/em> which notionally makes no sense because why would you bother if it is going to be ignored. Then this will trigger the process of a conditional operation which uses the “truth” of the the CY-IN as a signal which will either inhibit or allow the write back to the Register File from the ALU output.<\/p>\n
    But for this to all work nicely we first need to re-order the selection table for the CY-IN select. So in my PISC 1.0c version this select table looks like this (obviously at this point any code Brad wrote for his 1.0a version is not going to run on mine ;-).<\/p>\n
    00 = \"1\" (logic level low)\r\n01 = CY\r\n10 = EQ\r\n11 = \"0\" (logic level high)<\/pre>\n
    Also note that this change plays with the order of the “0” and “1” as well. Which means that we must change the hard coded Fetch Instruction such that it is now:<\/p>\n
    10111111 10000000 <\/strong>or $BF80<\/strong><\/p>\n
    The re-ordering of the “1” and “0” gives us some very important additional functionality which I’ll get to shortly. But was not strictly required for conditional jumps.<\/p>\n
    So this now gives us a instruction table subset for bits IR:6, IR:5 and IR:4 that looks like this:<\/p>\n
    00-1 = Valid Logic Function write to Register File enabled WEA\/ = Low\r\n01-1 = Conditional Write to Register File dependent on CY status bit\r\n10-1 = Conditional Write to Register File dependant on EQ status bit\r\n11-1 = Write back to Register File is forcibly inhibited WEA\/ = High<\/pre>\n
    The last combination in the table “11-1” is the reason for swapping the order of the “0” and “1” around. This arrangement enables us to programmatically stop PISC from writing the result of an ALU Logic Operation back to the A-Register. When would you wish to do this? When you are performing a logic operation and you are only interested in setting the Flags (EQ & CY). But *do not*<\/strong> wish to destroy the contents of your A-Register while doing so. 
    \n<\/em><\/p>\n
    Normally PISC 1.0a will always write the result of the ALU logic function back into the register specified for the Address Bus or ALU “A” input (same thing). There is no way of stopping this. Now there is, so a instruction like this:<\/p>\n
    CMP\u00a0\u00a0 R0,R4<\/p><\/blockquote>\n
    Which is “Compare registers R0 and R4 and set the EQ flag if equal”. Can be crafted such that the contents of register R0 is not overwritten by the operation. Quite a useful feature! Sadly this only works for ALU Logic operations and not for Arithmetic operations. Oh well, I’ll take those features I can get cheaply.<\/p>\n
    So what do the actual PISC Assembler instructions look like? We can now craft an instruction like this:<\/p>\n
    MOV\u00a0\u00a0 R7,R4\u00a0\u00a0\u00a0 IF EQ<\/p><\/blockquote>\n
    Translated: Copy the contents of R4 to R7 (R7 being the Program Counter) but only if the EQ flag is set “1” (logic level low). If the copy is successful then a jump to the location in R4 happens. If the copy is inhibited then the next instruction is executed. Conditional branch.<\/p>\n
    Of course my PISC Assembler allows you to normally code this instruction as something like:<\/p>\n
    JEQ\u00a0\u00a0\u00a0 LOOP<\/p><\/blockquote>\n
    Jump if Equal to address LOOP.<\/p>\n
    So how expensive is the modification? Three gates (besides the re-wiring mentioned above). Looks like this:<\/p>\n
    \"\"<\/a><\/p>\n","protected":false},"excerpt":{"rendered":"
    The first of the “Glaring Deficiencies” in need of a solution was the missing conditional branch (jump). This is how I went about solving it. Firstly a review of how PISC encodes an instruction:- \u00a0\u00a0\u00a0\u00a0\u00a0\u00a0\u00a0\u00a0\u00a0\u00a0\u00a0\u00a0\u00a0\u00a0\u00a0\u00a0\u00a0\u00a0\u00a0\u00a0\u00a0\u00a0\u00a0\u00a0\u00a0\u00a0\u00a0\u00a0\u00a0 IR 15:0 MRD\u00a0 MWR ARGx3 … Continue reading →<\/span><\/a><\/p>\n","protected":false},"author":1,"featured_media":0,"comment_status":"closed","ping_status":"open","sticky":false,"template":"","format":"standard","meta":{"footnotes":""},"categories":[1],"tags":[],"class_list":["post-551","post","type-post","status-publish","format-standard","hentry","category-uncategorized"],"_links":{"self":[{"href":"https:\/\/www.vk2sja.org\/piffle\/wp-json\/wp\/v2\/posts\/551","targetHints":{"allow":["GET"]}}],"collection":[{"href":"https:\/\/www.vk2sja.org\/piffle\/wp-json\/wp\/v2\/posts"}],"about":[{"href":"https:\/\/www.vk2sja.org\/piffle\/wp-json\/wp\/v2\/types\/post"}],"author":[{"embeddable":true,"href":"https:\/\/www.vk2sja.org\/piffle\/wp-json\/wp\/v2\/users\/1"}],"replies":[{"embeddable":true,"href":"https:\/\/www.vk2sja.org\/piffle\/wp-json\/wp\/v2\/comments?post=551"}],"version-history":[{"count":28,"href":"https:\/\/www.vk2sja.org\/piffle\/wp-json\/wp\/v2\/posts\/551\/revisions"}],"predecessor-version":[{"id":583,"href":"https:\/\/www.vk2sja.org\/piffle\/wp-json\/wp\/v2\/posts\/551\/revisions\/583"}],"wp:attachment":[{"href":"https:\/\/www.vk2sja.org\/piffle\/wp-json\/wp\/v2\/media?parent=551"}],"wp:term":[{"taxonomy":"category","embeddable":true,"href":"https:\/\/www.vk2sja.org\/piffle\/wp-json\/wp\/v2\/categories?post=551"},{"taxonomy":"post_tag","embeddable":true,"href":"https:\/\/www.vk2sja.org\/piffle\/wp-json\/wp\/v2\/tags?post=551"}],"curies":[{"name":"wp","href":"https:\/\/api.w.org\/{rel}","templated":true}]}}