PISC – (Pathetic Instruction Set Computer)
This is my version of PISC an educational computer designed by Brad Rodriguez. The entire computer and CPU are scratch built using only standard TTL integrated circuits. The original v1.0a design can be found Brad’s website here:-
My enhanced 1.0c version adds some additional functionality not found in the original.
My PISC 1.0c version at a glance…
- 16 bit TTL CPU.
- 4 x 74181 ALU IC’s tied together, each looking after 4 bits for 16 bits of computation in a single cycle.
- 256 Kilo-words of memory, 128k EEPROM and 128k RAM. Memory is bank switched into 4 x banks of 16K x 16 bit words.
- Directly addressable memory space is 64K x 16 bit words.
- Each instruction (operational) code is only 16 bits wide. With nearly all control signals being horizontally encoded in only 16 bits. There is NO microcode or microcode sequencer!
- I did mention that PISC is a 16 bit machine?
- The machine only has two CPU flags, EQ (Equality) and CY (Carry). In practice I have not found this to be problem while programming.
- The system runs at 4 MHz with one wait state introduced for slower 8 bit I/O devices.
- The machine operates in two distinct cycles, Fetch and Execute. So the effective time spent executing program code is one half of the 4 MHz clock i.e 2.0 MHz. The other half is spent executing the fetch instruction for the next opcode.
- I guess it would be fair to characterize PISC as an extreme example of a RISC style architecture?
- There is a 7 slot 16 bit master bus.
- A four slot CPU internal bus (a 50 pin SCSI cable) that ties the cards making up the CPU together.
- Additionally there is a 7 slot 8 bit I/O peripherals bus.
- A single shared interrupt is supported for I/O peripheral cards with card priority determined by the slot it is plugged into.
There are 8 x 16 bit registers (R0..R7):
- Register R7 is dedicated to functioning as the Program Counter (PC). Software can write to R7 and it will then auto increment on each Fetch cycle.
- Register R6 is used to hold the Interrupt Vector and during an Interrupt Service Routine (ISR) it acts as the Program Counter. It can be used as a general purpose register if Interrupts are disabled.
- Register R5 is used to implement a system Stack in software. So it holds the current Top of Stack pointer (TOS) address.
- Register R4 is used internally by my “hacked-together” home brew Assembler, as a general purpose “scratch pad” variable.
- This leaves R0 to R3 truly free, as general purpose registers for programmers.
- The system is little endian.
- The stack grows UP! An unusual choice I know, and it could easily have been done either way. The stack runs into I/O space at the top of memory which causes a NMI. So any stack overrun is captured.
- A Shift Register board adds the following shift operations:
- Simple bit-wise Right Shift (this logic function is missing from the 74181 ALU).
- Arithmetic Right Shift
- High order 8 bit for Low order 8 bit swap (which makes dealing with 8 bit byte values much easier! :-).
- Input/Output devices are memory mapped from $FF00 to $FFFF
- Operational I/O devices include a 2651 RS232 serial port and a 7-Seg LED with keypad control panel interface.
Currently my PISC is programmed (cross platform) using a PC in either an Assembler or a Pascal like language derived and extended from PL/0 which I call PL/0+. With most sincere gratitude to Professor Niklaus Wirth! – “Algorithms + Data Structures = Programs” (1975). It was simple enough for someone without a Computer Science degree to understand and powerful enough to do something useful after some simple extensions.
Program machine code (or byte-code in the case of PL/0+) can be uploaded to the machine via the serial port using a modified version of the Intel hex file format. The loader being part of the PISC Monitor.
Both my PISC Assembler and PL/0+ language are written in Free Pascal.
- Sample assembler code here: pmon-dev.asm
- Assembler listing file for the source above: pmon-dev.lst
- Sample pl/0+ program here: trek.pl0
More coming soon…